Program

Sunday, May 12th

14:00- Registration

15:00-17:00 Special Session in ASYNC2019
18:00- Welcome reception



Monday, May 13th

8:00- Registration

8:30-9:00 OPENING REMARKS

9:00-10:00 Keynote 1
10:00-10:30 BREAK

10:30-11:50 Session 1: Tools for Design Exploration I
  • AMC: An Asynchronous Memory Compiler
    Samira Ataei and Rajit Manohar
  • Design and FPGA-implementation of Asynchronous Circuits Using Two-phase Handshaking
    Adrian Mardari, Zuzana Jelcicová and Jens Sparsø
  • Unified (A)Synchronous Circuit Development   Fresh Idea
    Philipp Paulweber, Jürgen Maier and Jordi Cortadella
11:50-13:30 LUNCH @ 12F Sky Banquet

13:30-14:20 Session 2: Tools for Design Exploration II
  • Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits
    Yi-Fan Evan Chang, Ruei-Yang Huang and Jie-Hong R. Jiang
  • PinTu: An Innovative Asynchronous EDA Tool for Xilinx FPGA   Fresh Idea
    Anping He, Yi Zuo, Li Wen, Zhi Wang, Ning Zhou, Zhihua Feng, Jinzhao Wu and Winston Tian
14:20-14:30 SHORT BREAK

14:30-16:10 Session 3: Networks and Systems on Chip
  • A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
    Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally and Brucek Khailany
  • Two-Phase Asynchronous to Synchronous Interfaces for an Open-Source Bundled-Data Flow   Fresh Idea
    Ameer Abdelhadi, Dake Chen, Huimei Cheng, Gourav Datta, Yang Zhang, Peter A. Beerel and Mark R. Greenstreet
  • A Transmission Line Enabled Clockless Network-On-Chip
    Mackenzie J. Wibbels, Shomit Das, Dheeraj Singh Takur, Vankata Nori and Kenneth S. Stevens
  • Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone   Industrial
    Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal and Ramesh Chauhan
16:10-16:40 BREAK

16:40-18:30 Session 4: Asynchronous Circuits Conquering the World
  • ASIE: An Asynchronous SNN Inference Engine for AER Events Processing
    Ziyang Kang, Lei Wang, Shasha Guo, Rui Gong, Yu Deng and Qiang Dou
  • A Variable Bitwidth Asynchronous Dot Product Unit   Fresh Idea
    Jonny Edwards, Adrian Wheeldon, Rishad Shafik, and Alex Yakovlev
  • AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology   Industrial
    Mickael Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey and Michel Laurence
  • An FPGA Implementation of a Time-to-Digital Converter based on Self-Timed Ring Oscillator   Fresh Idea
    Assia El-Hadbi, Oussama Elissati, Abdelkarim Cherkaoui and Laurent Fesquet
  • Asynchronous Pixels for Astronomical Imaging   Fresh Idea
    Yi Hu, Abu-Bakar Raja, Ketan Mayer-Patel and Montek Singh
18:30-19:30 Session 5: Demos and Posters
  • Combining Reconfiguration and Instruction Computations With An Asynchronous Method  Poster/Demo
    Anping He, Pengfei Li, Jiling Zhang, Zhihua Feng and Jay Yan



Tuesday, May 14th

8:00- Registration

8:30-9:30 Keynote II
9:30-10:00 BREAK

10:00-11:00 Session 6: General Synthesis
  • Synthesis from Waveform Transition Graphs
    Alberto Moreno, Danil Sokolov and Jordi Cortadella
  • Asynchronous Signalling Processes
    Rajit Manohar and Yoram Moses
11:00-12:20 Session 7: Timing Analysis and Validation
  • Transistor-Level Analysis of Dynamic Delay Models
    Jürgen Maier, Matthias Függer, Thomas Nowak and Ulrich Schmid
  • From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits
    Grégoire Gimenez, Jean Simatic and Laurent Fesquet
  • Delay lines test method for the Blade Template   Fresh Idea
    Felipe A. Kuentzer, Leonardo R. Juracy, Matheus T. Moreira and Alexandre M. Amory
12:20-13:30 LUNCH @ 2F Chef's Recipe

13:30-14:30 Session 8: Verification
  • Verifying Timed, Asynchronous Circuits using ACL2
    Yan Peng and Mark R. Greenstreet
  • A Hierarchical Approach to Self-Timed Circuit Verification
    Cuong Chau, Warren Hunt, Matt Kaufmann, Marly Roncken and Ivan Sutherland
14:30-15:50 Session 9: Cycle and Arbitration Timing
  • Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
    Marcos L.L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira and Ney L.V. Calazans
  • Desynchronization Should Target 3-phase Latch-based Designs   Fresh Idea
    Huimei Cheng and Peter A. Beerel
  • Efficient Metastability Characterization for Schmitt-Triggers
    Jürgen Maier and Andreas Steininger
16:00- Social events (Excursion and Banquet)



Wednesday, May 15th

8:00- Registration

8:30-9:30 Keynote III
9:30-10:00 BREAK

10:00-11:10 Session 10: Resilience to Attacks and Errors
  • Hardware Trojan Insertion and Detection in Asynchronous Circuits
    Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa and Masashi Imai
  • Soft error detection and correction architecture for asynchronous bundled data designs   Fresh Idea
    Felipe Kuentzer and Milos Krstic
  • Island-based Random DVS to Combat Power Attacks   Fresh Idea
    Dake Chen and Peter A. Beerel
11:10-11:45 BREAK

11:45-12:00 BEST PAPER AWARD, CLOSING REMARKS
  • LUNCH