Keynote 1 (May 13th)

Machine Learning at the Edge
Prof. Warren J. Gross
McGill University, Canada

Abstract - Deep neural networks have gone through a recent rise in popularity, achieving state-of-the-art results in various fields, including image classification and speech recognition. This talk will describe recent progress in the design and hardware implementation of machine learning algorithms for edge computing. The first part of the talk will discuss architectures for machine learning hardware under limited hardware resources and tight power and latency constraints. The second part of the talk will discuss the need for automated tools to solve the difficult problem of designing neural networks under complexity constraints and will describe a design-space-exploration tool that automatically discovers good neural network models with efficient hardware implementations.

Warren J. Gross Warren J. Gross received the B.A.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1996, and the M.A.Sc. and Ph.D. degrees from the University of Toronto, Toronto, ON, Canada, in 1999 and 2003, respectively. He is a Professor and Louis-Ho Faculty Scholar in Technological Innovation in the Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada. He currently serves as Chair of the Department. His research interests are in the design and implementation of signal processing systems and custom computer architectures. Dr. Gross served as the Chair for the IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems. He served as the General Co-Chair for the IEEE GlobalSIP 2017 and the IEEE SiPS 2017 and the Technical Program Co-Chair for SiPS 2012. He also served as an Organizer for the Workshop on Polar Coding in Wireless Communications at WCNC 2018 and WCNC 2017, the Symposium on Data Flow Algorithms and Architecture for Signal Processing Systems (GlobalSIP 2014), and the IEEE ICC 2012 Workshop on Emerging Data Storage Technologies. He served as an Associate Editor for the IEEE Transactions on Signal Processing and as a Senior Area Editor. He is a Licensed Professional Engineer in the Province of Ontario.

Keynote 2 (May 14th)

Asynchronous Superconducting Digital Circuits
Prof. Nobuyuki Yoshikawa
Yokohama National University, Japan

Abstract - Superconducting single-flux-quantum (SFQ) circuits utilize a picosecond-width voltage pulse as bit information. Because of their high clock frequency beyond several tens of GHz with extremely energy-efficient switching operation, they are thought to be a promising candidate of post-CMOS devices for realizing high-performance computing systems. Their logical bit information is determined by existence or absence of an SFQ pulse during the clock period; therefore every gate has to be clocked by an SFQ pulse. Since the propagation delay of SFQ gates is sensitive to the change of the circuit parameters as well as thermal noise, the design of SFQ digital circuits at clock frequencies beyond tens of GHz is challenging. So far a wide range of asynchronous clocking schemes from completely asynchronous to partially asynchronous have been proposed, and several demonstrations of asynchronous SFQ digital circuits have been reported. After reviewing the asynchronous SFQ digital circuits, this talk will discuss appropriate timing approaches for making a large-scale SFQ digital system.

Nobuyuki Yoshikawa Nobuyuki Yoshikawa received the Ph.D. degree in electrical and computer engineering from Yokohama National University, Japan in 1989. Currently he is a professor in the Department of Electrical and Computer Engineering, Yokohama National University. He is also a chair of the Superconducting Electronics Committee of the Japan Society for the Promotion of Science (JSPS) and the Technical Committee on Metal and Ceramics of the Institute of Electrical Engineering of Japan. His research interests include superconductive devices and their application in digital and analog circuits. He is also interested in single-electron-tunneling devices, quantum computing devices, and cryo-CMOS devices. He has led the Superconductivity Electronics Group in Yokohama National University. He is an expert in the field of superconductivity electronics and the foremost active researcher of superconducting logic. He has published more than sixty articles on single-flux-quantum (SFQ) and adiabatic quantum flux parametron (AQFP) circuits or closely related topics in the past five years alone.

Keynote 3 (May 15th)

Design and Architecture for Quantum Information Systems
Prof. Kae Nemoto
National Institute of Informatics, Japan

Abstract - In the last few years, huge efforts to realize superconducting-based quantum computers have been undertaken worldwide. These quantum computers are all monolithic with tens of physical qubits designed on a superconducting 2D-chip. Although they can perform quantum computation, due to the noise on the physical qubits, their quantum supremacy (the promised computational power beyond the capabilities of the conventional computers) has not yet been demonstrated. A fault-tolerant implementation will ensure such quantum supremacy, however it requires a far larger number of qubits and the scalable technology for quantum computation has to be realized first.
   There is another route to a large-scale quantum computation, which is distributed in nature. Distributed quantum information processing has been shown to be more scalable and easily accommodates the advantages that arise from the close relation between quantum computation and communication. In this talk, we first introduce the concept of distributed quantum information processing, discussing the advantages and disadvantages of such an approach. Going through typical synchronous and asynchronous system designs for quantum communication, we will then discuss the trade-off between quantum and classical recourses. Quantum computation is usually designed based on synchronous control, however there are possibilities that asynchronous control could help distributed quantum computation to be faster reducing the waiting time of each of the physical qubits. Although asynchronous control in quantum computation is largely unexplored, it could be hugely beneficial by lowering the physical requirements to realize distributed quantum computation.

Kae Nemoto Kae Nemoto is a Professor in the Principles of Informatics Research Division at the National Institute of Informatics (NII) in Tokyo, as well as at the Graduate University for Advanced Studies (SOKENDAI). She received her PhD from Ochanomizu University in Tokyo in 1996. After several years in Australia and the UK as a research fellow, she took a position at NII in 2003. She is currently the director of the Global Research Center for Quantum Information Science at NII while also serving as the Japanese director for the Japanese-French Laboratory for Informatics. Her current research interests include system design for quantum computation and communications, quantum metrology, the implementation of quantum information devices, quantum network science, and quantum complex systems. She is a Fellow of the APS (US) and IoP (UK).